module spart(input clk, rst,                       //basic signals
	     input iocs, iorw, input [1:0] ioaddr, //inputs from processor
	     output rda, tbr,                      //outputs to processor
	     inout [7:0] databus,           //bidirectional to/from processor
	     output txd,                           //output to serial
	     input rxd);                         //input from serial
   wire [7:0] 	    recbuf, busout;
   wire            transrateen, recvrateen;
   
   busint bus(.iocs(iocs), .iorw(iorw), .rda(rda), .tbr(tbr), .recbuf(recbuf), .out(busout), 
   			.databus(databus), .ioaddr(ioaddr));
   baudgen baud(.clk(clk), .rst(rst), .iorw(iorw), .iocs(iocs), .ioaddr(ioaddr), 
   			 .divin(busout), .transrateen(transrateen), .recvrateen(recvrateen)
			 );
   transmit xmit(.rateen(transrateen), .clk(clk), .rst(rst), .iocs(iocs),
   			  .iorw(iorw), .data(busout), .ioaddr(ioaddr), .tbr(tbr), .txd(txd));

   recv rec(.clk(clk), .rst(rst), .iocs(iocs), .iorw(iorw), .ioaddr(ioaddr),
   		  .rda(rda), .rxd(rxd), .recbuf(recbuf), .recvrateen(recvrateen));
   
   


endmodule
